Hacking with a CPLD board
A long time ago, I bought a Binary Explorer Board
(also called Bora board) as I wanted to learn FPGA and CPLD programming. But I did not use it and the board sat on my shelf for a long time. Now I wanted to finally put it to use, but many years after the board's discontinuation, most documentation has vanished and the little that is left is only for Windows.
Because I wanted to use this board anyway, I wrote this tutorial on how to the program and use the it on Linux.
The Binary Explorer Board
Getting it to run
My board didn't work when plugged in and didn't register an USB device: the firmware probably got corrupted from sitting so long on my shelf without an ESD bag, but we can fix this.
Tip: if you don't want to solder the ISP connector and reset pins, you can use tweezers or small crocodile clips to short the pins.
- Get the firmware file: borajtag_0.2_at90usb162.hex
- Plug the board in
- Short the two "boot" pins
- Short the two topmost pins of the ISP connector (right of the Atmel chip)
- Remove both shorts
- Device will be initialized as "Atmel Corp. at90usb162 DFU bootloader"
We can now use
to flash the default firmware:
$ dfu-programmer at90usb162 erase
$ dfu-programmer at90usb162 flash borajtag_0.2_at90usb162.hex
4502 bytes used (36.64%)
Unplug and plug the board, and it should be detectable again:
Bus 003 Device 003: ID 03eb:204f Atmel Corp. LUFA Generic HID Demo Application
Getting the required tools
We will need:
Programming the board
While some new FPGAs can be programmed using an open-source toolchain, it isn't the case of the XC9572XL CPLD this board uses. Xilinx ISE, the old IDE used for developping on Xilinx FPGAs and CPLDs, is therefore required (a 25 GB install!)
I will not detail the usage of Xilinx ISE, as there are already very good tutorials on this on the internet, but the sample project countains example files which can be used to quickly test the board.
As the board doesn't use the stardard Xilinx JTAG interface, batch scripts are used to program the XC9572XL CPLD. these scripts were only provided for Windows. Here are the Linux equivalents:
: produce a .svf file that the JTAG programmer can use to program the CPLD:
echo setMode -bscan >> commandToImpact.cmd
echo setCable -p svf -file $1.svf >> commandToImpact.cmd
echo addDevice -p 1 -file $1.jed >> commandToImpact.cmd
echo erase -p 1 >> commandToImpact.cmd
echo program -p 1 >> commandToImpact.cmd
echo quit >> commandToImpact.cmd
/opt/Xilinx/12.4/ISE_DS/ISE/bin/lin64/impact -batch commandToImpact.cmd
To actually program the board, we need to patch a specific version of urjtag
. Start by downloading urjtag 0.10
and then patch and compile the source code:
$ wget https://gist.githubusercontent.com/timwu/3127865/raw/ae1e6e225f4e2a48b7d3350e2cfc80face6647e2/urjtag-0.10-opendous.patch
$ tar xzf urjtag-0.10.tar.gz
$ patch -p0 < urjtag-0.10-opendous.patch
$ cd urjtag-0.10
$ make -j4
$ sudo make install
This will install the
program into /usr/local/bin/jtag, which is used to program to execute the .svf programming file. To finalize the install, copy the urjtag-windows-dist/data/xilinx/xc9572xl_vq44/STEPPINGS file from the sample project to /usr/local/share/urjtag/xilinx/xc9572xl_vq44/STEPPINGS.
Otherwise, the CPLD will not be recognized. You can now use
to program the CPLD:
UrJTAG 0.10 #1502
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors
UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.
WARNING: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.
jtag> cable opendous
IR length: 8
Chain length: 1
Device Id: 01011001011000000100000010010011 (0x0000000059604093)
jtag> svf io_connections.svf progress
The CPLD is now programmed with your chosen .svf file.
Addendum: sample Verilog code
This is a basic Verilog example to verify that the board is correctly working. The LED1 will be on of the EN(able) switch (SW1) is on and any of the SW2 or SW3 switch (A and B respectively) is on.
Timing diagram for this example (in ISim)
Test.v: example Verilog file
module Test(A, B, ENABLE, S);
input A, B, ENABLE;
assign S = ENABLE & (A | B);
Test.ucf: corresponding constraints file
NET ENABLE LOC=P8;
NET A LOC=P7;
NET B LOC=P6;
NET S LOC=P27;
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